datasheet low skew clock inverter and divider ics548-03 idt?/ics? low skew clock inverter and divider 1 ics548-03 rev e 071807 description the ics548-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. using our patented phase-locked loop (pll) techniques, the device operates from a frequency range of 10 mhz to 120 mhz in the pll mode, and up to 160 mhz in the non-pll mode. in applications that need to ma intain low phase noise in the clock tree, the non-pll (when s3=s2=1) modes should be used. this chip is not a zero delay buffer. many applications may be able to use the ics527 for zero delay dividers. features ? packaged in 16-pin soic (150 mil) ? input clock up to 160 mhz in the non-pll mode ? provides clock outputs of clk, clk , and clk/2 ? low skew (500 ps) on clk, clk , and clk/2 ? all outputs can be tri-stated ? entire chip can be powered down by changing one or two select pins ? 3.3 v or 5.0 volt operating range ? available in commercial and industrial temperature ranges ? available in pb (lead) free package block diagram input buffer clk clock synthesis and divider circuitry clock input s3:s0 4 vdd 2 gnd 2 clk clk/2 oe (all outputs)
ics548-03 low skew clock inverter and divider clock divider idt?/ics? low skew clock inverter and divider 2 ics548-03 rev e 071807 pin assignment clk, clk , and clk/2 select table (mhz) 12 1 11 2 10 3 9 iclk 4 vdd 5 vdd 6 dc 7 s3 8 gnd dc clk clk gnd oe s2 s1 16 15 14 13 s0 dc clk/2 s3 s2 s1 s0 clk, clk clk/2 pll input range 0 0 0 0 low low off power down 0 0 0 1 input/4 input/8 on 20 - 120 0 0 1 0 input input/2 on 20 - 120 0 0 1 1 input/2 input/4 on 20 - 120 0 1 0 0 low low off power down 0 1 0 1 input x 2 input on 20 - 60 0 1 1 0 input/5 input/10 on 20 - 120 0 1 1 1 input/3 input/6 on 20 - 120 1 0 0 0 low low off power down 1 0 0 1 input/4 input/8 on 10 - 60 1 0 1 0 input input/2 on 10 - 60 1 0 1 1 input/2 input/4 on 10 - 60 1 1 0 0 low low off power down 1 1 0 1 input/6 input/12 off 0 - 160 1 1 1 0 input/8 input/16 off 0 - 160 1 1 1 1 input/2 input/4 off 0 - 160
ics548-03 low skew clock inverter and divider clock divider idt?/ics? low skew clock inverter and divider 3 ics548-03 rev e 071807 pin descriptions external components the ics548-03 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01f should be connected between pins 3 and 5, as close to the device as possible. connect pin 2 directly to pin 3, and pin 6 directly to pin 5. a series termination resistor of 33 ? should be used on all clock outputs, as close to the device as possible. leave any unused clock outputs floating. there are no pull-up resistors on the input pins, and they may be connected directly to vdd or ground. pin number pin name pin type pin description 1 iclk input clock input. 2 vdd power connect to 3.3 v or 5 v. 3 vdd power connect to 3.3 v or 5 v. 4 s3 input clock select 3. see table on page 2. 5 gnd power connect to ground. 6 gnd power connect to ground. 7 s2 input clock select 2. see table on page 2. 8 s0 input clock select 0. see table on page 2. 9 s1 input clock select 1. see table on page 2. 10 oe input output enable. tri-states all clock outputs when low. 11 clk/2 output clock output divided by 2. see table on page 2. 12 clk output clock output. see table on page 2. 13 clk output inverted clock output. see table on page 2. 14 dc ? don?t connect. do not connect anything to this pin. 15 dc ? don?t connect. do not connect anything to this pin. 16 dc ? don?t connect. do not connect anything to this pin.
ics548-03 low skew clock inverter and divider clock divider idt?/ics? low skew clock inverter and divider 4 ics548-03 rev e 071807 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics548-03. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd = 3.3 v, ambient temperature 0 to +70 c or -40 c to +85 c , unless stated otherwise item rating supply voltage, vdd (referenced to gnd) -0.5 v to 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature (commercial) 0 +70 c ambient operating temperature (industrial) -40 +85 c power supply voltage (measured in respect to gnd) +3.13 +5.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.13 5.5 v input high voltage v ih iclk only (pin 1) (vdd/2)+1 vdd/2 v input low voltage v il iclk only (pin 1) vdd/2 (vdd/2)-1 v input high voltage v ih all other inputs 2 v input low voltage v il all other inputs 0.8 v output high voltage, cmos level v oh i oh = -8 ma vdd-0.4 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v operating supply current, 100 mhz clock idd s3=s2=s0=0, s1=1 20 ma short circuit current i os each output 50 ma input capacitance c in all inputs 5 pf
ics548-03 low skew clock inverter and divider clock divider idt?/ics? low skew clock inverter and divider 5 ics548-03 rev e 071807 ac electrical characteristics vdd = 3.3 v, ambient temperature 0 to +70 c, unless stated otherwise note 1: the phase relation ship between input and output clocks can change at power up. use the ics570 or ics527 zero delay buffers for a guaranteed phase relationship. thermal characteristics parameter symbol conditions min. typ. max. units input frequency, clock input, pll on f in 10 120 mhz input frequency, clock input, pll off f in 0160mhz output frequency (see table on page 2) f out mode dependent 0 120 mhz output clock rise time t or 0.8 to 2.0 v 0.84 ns output clock fall time t of 2.0 to 0.8 v 0.74 ns output clock duty cycle t dc at vdd/2 45 49 to 51 55 % output enable time, oe high to output on 50 ns output disable time, oe to tri-state 50 ns absolute clock period jitter. pll modes deviation from mean 150 ps one sigma clock period jitter, pll modes 60 ps output clock skew for clk, clk , or clk/2 at vdd/2 350 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 120 c/w ja 1 m/s air flow 115 c/w ja 3 m/s air flow 105 c/w thermal resistance junction to case jc 58 c/w
ics548-03 low skew clock inverter and divider clock divider idt?/ics? low skew clock inverter and divider 6 ics548-03 rev e 071807 package outline and package dimensions (16-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both ac curacy and reliability, integrat ed device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for us e in normal commercial applications. any ot her applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended wi thout additional processing by idt. idt reserves the right to change any circuitry or specifications wi thout notice. idt does not authorize or warrant any idt product for use in life sup port devices or critical medical instruments. part / order number marking shipping packaging package temperature 548m-03 ics548m-03 tubes 16-pin soic 0 to +70 c 548m-03t ics548m-03 tape and reel 16-pin soic 0 to +70 c 548m-03lf 548m-03lf tubes 16-pin soic 0 to +70 c 548m-03lft 548m-03lf tape and reel 16-pin soic 0 to +70 c 548m-03i ics548m-03i tubes 16-pin soic -40 to +85 c 548M-03IT ics548m-03i tape and reel 16-pin soic -40 to +85 c 548mi-03lf 548mi-03lf tubes 16-pin soic -40 to +85 c 548mi-03lft 548mi-03lf tape and reel 16-pin soic -40 to +85 c index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 9.80 10.00 .3859 .3937 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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